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| THURSDAY, June 10, 2004, 4:30 PM - 6:00 PM | Room: 4 | ||
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TOPIC AREA: LOGIC DESIGN AND TEST | ||
| SESSION 55 | |||
| CAD for Reconfigurable Computing | |||
| Chair: Jason Cong - Magma Design Automation, Inc., Los Angeles, CA | |||
| Organizers: Jens Palsberg, Scott Hauck | |||
| By combining the fast reconfiguration of microprocessors with the high-performance of hardware, FPGAs open up new challenges to the CAD designer. This session considers fast algorithms for reconfigurable computing as well as operating systems support for such systems. | |||
 55.1 |
Virtual Memory Window for Application-Specific Reconfigurable Coprocessors |
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| Speaker(s): | Miljan Vuletic - Swiss Federal Institute of Tech., Lausanne, Switzerland | ||
| Author(s): | Miljan Vuletic - Swiss Federal Institute of Tech., Lausanne, Switzerland Laura Pozzi - Swiss Federal Institute of Tech., Lausanne, Switzerland Paolo Ienne - Swiss Federal Institute of Tech., Lausanne, Switzerland | ||
| 55.2 | Dynamic FPGA Routing for Just-in-Time FPGA Compilation | ||
| Speaker(s): | Roman Lysecky - Univ. of California, Riverside, CA | ||
| Author(s): | Roman Lysecky - Univ. of California, Riverside, CA Frank Vahid - Univ. of California, Riverside, CA Sheldon X.-D. Tan - Univ. of California, Riverside, CA | ||
| 55.3 | An Efficient Algorithm for Finding Empty Space for Online FPGA Placement | ||
| Speaker(s): | Manish Handa - Univ. of Cincinnati, Cincinnati, OH | ||
| Author(s): | Manish Handa - Univ. of Cincinnati, Cincinnati, OH Ranga Vemuri - Univ. of Cincinnati, Cincinnati, OH | ||
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